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Features
* Fulfills IEC 1036, Class 1 Accuracy Requirements * Fulfills IEC 687, Class 0.5 and Class 0.2 Accuracy, with External Temperature * * * * * * * * * * *
Compensated Voltage Reference Simultaneous Active, Reactive and Apparent Power and Energy Measurement Power Factor, Frequency, Voltage and Current Measurement Single and Poly Phase Operation Three Basic Operating Modes: Stand-Alone Mode, Microprocessor Mode and MultiChannel Mode Flexible Interfacing, 8-bit Microprocessor Interface, 8-bit Status Output and Eight Impulse Outputs Calibration of Gain and Phase Error Compensation of the Non-Linearity of Low Power Measurement Adjustable Starting Current and Meter Constant Measurement Bandwidth of 1000 Hz Tamper Proof Design Single +5V Supply
Chip Set Solution for Watt-Hour Meters AT73C500 with AT73C501 or AT73C502
Description
A two chip solution, consisting of AT73C500 and AT73C501 (or AT73C502), offers all main features required for the measurement and calculation of various power and energy quantities in static Watt-hour meters. The devices operate according to IEC1036, class 1, specification. IEC 687, class 0.5 and 0.2 requirements are fulfilled when used with external temperature compensated voltage reference. The AT73C501 contains six, high-performance, Sigma-Delta analog-to-digital converters (ADC). The AT73C500 is based on an efficient digital signal processor (DSP) core and it supports interfacing both with the AT73C501 and with an external microprocessor. The AT73C500 DSP can also be used with the differential input ADC, AT73C502. With this chipset, only a minimum of discrete components is required to develop products ranging from simple domestic Watt-hour meters to sophisticated industrial meters. The chipset can be used in single-phase as well as in poly-phase systems. The DSP core of the AT73C500 is easy to configure. By changing the mode of the AT73C500, the device can be operated in a stand-alone environment or be used with a separate control processor. It is also possible to configure the circuit to perform the functions of three independent single phase Wh meters. The chips support calibration of gain and phase error. All calibrations are done in the digital domain and no trimming components are needed. The calibration coefficients are either stored in an EEPROM memory or supplied by an external microprocessor. (continued)
Rev. 1035A-08/98
1
Figure 1. Block diagram of the AT73C500 chipset in stand-alone configuration
EXTERNAL CONNECTOR
L1 L2 L3
VREF BGD VI1 VI2 VI3 CI1 CI2 CI3
VDA VDDA
VCC BRDY PFAIL
VCC STROBE RD/WR ADDR1 -VArh +VArh -Wh +Wh +Wh -Wh +VArh -VArh
AT73501
SIX SINGLE-ENDED, INDEPENDENT SIGMA-DELTA CONVERTERS
IRQ0 ACK DATA CLKR CLK & IRQ1 SIN SCLK
AT73500
ADDR0
SOUT1 SOUT0
L1
DEDICATED DSP FOR ENERGY METERING
DATA BUS
RESET CS AGND XRES
STATUS BUS
L2
XI XO MODE VSA VSSA GND 1 GND 1 &
L3
TAMP STUP L3 L2 L1 FAIL DATRDY INI
&
CS SK DI
AT93C46
DO
MODE2 MODE1 MODE0
RESET
1
EEPROM 128*8 bit
1 1 1 1
The AT73C500 is programmed to measure active, reactive and apparent phase powers. Phase factors, phase voltages, phase currents and line frequency are also measured, simultaneously. Based on the individual phase powers, total active power is determined. The power values are calculated over one-line frequency cycle. The negative and positive results are accumulated in different registers, which allows for separate billing of imported and exported active energy. Also, the reactive results are sorted depending on whether capacitive or inductive load is applied.
Eight pulse outputs are provided. Each billing quantity (+Wh, -Wh, +VArh, -Varh) is supplied with its own meter constant output, as well as a display counter output. In multi-channel mode, AT73C500 performs the functions of three independent single phase Wh meters and three impulse outputs are available, one for each meter element. All measurement information is available on an 8-bit microprocessor bus. The results are output in six packages, 16 bytes each. Mode and status information of the meter is also transferred with each data block.
Figure 2. Block diagram of the AT73C500 chipset in microprocessor configuration
L1 L2 L3
VREF BGD VI1 VI2 VI3 CI1 CI2 CI3 PFAIL VDA VDDA VCC BRDY VCC STROBE RD/WR ADDR1
AT90Sxx
AT73501
SIX SINGLE-ENDED, INDEPENDENT SIGMA-DELTA CONVERTERS
IRQ0 ACK DATA CLKR CLK SIN SCLK IRQ1
AT73500
ADDR0
SOUT1 SOUT0
D
MICROCONTROLLER
DATRDY
L1
DEDICATED DSP FOR ENERGY METERING
DATA BUS
RESET CS AGND XRES
STATUS BUS B9
MODEM
GND 1 &
L2
XI XO MODE VSA VSSA GND
L3
LCD
RESET
1
MODE2 MODE1 MODE0
1 1 1 1
B14 B13 B12
EEPROM
2
AT73C500
AT73C500
Pin Description
AT73C501 Single-ended ADC
Figure 3. PLCC-28 package pin layout
XO 4 BGD CS VCC PFAIL AGND VCIN VREF 5 6 7 8 9 10 11 12 13 14 15 AIN4 16 AIN6 17 AIN1 18 AIN3 VSSA VDDA AIN2 XI 3 CLK CLKR ACK 2 1 28 FSR DATA 27 26 25 24 23 22 21 20 19 RESET
Analog Signals AIN1 AIN2
MODE GND PD VDA VSA AIN5
Pin 17 14 18 15 19 16 10
I/O I I I I I I I
Description Input to Converter #1 Input to Converter #2 Input to Converter #3 Input to Converter #4 Input to Converter #5 Input to Converter #6 Input to Voltage Monitoring Block
AIN3 AIN4 AIN5 AIN6 VCIN
Digital Control Signals BGD
Pin 5 6 22 24 25
I/O I I I I I
Description By-pass Control for Reference Voltage Chip Select Input Power Down Control for A/D Modulators Mode Selection Control Reset Input, Active High
Power Supply Pins VDDA VSSA VDA VSA AGND VREF VCC VGND Crystal Osc Signals XI XO
Pin 13 12 21 20 9 11 7 23
I/O PWR PWR PWR PWR PWR PWR PWR PWR
Description Analog Supply, Positive, +5V Analog Supply, Negative, 0V Analog Supply, Positive, +5V Analog Supply, Negative, 0V Analog Ground Reference Output Reference Voltage Output Digital Supply, Positive, +5V Digital Supply, Negative, 0V
CS PD MODE RESET Status Flags PFAIL
Pin 8
I/O O
Description Output of Voltage Monitoring Block
Output Bus Signals CLK
Pin 2 1 26 27 28
I/O O O O O O
Description Master Clock Output Serial Bus Clock Output Serial Data Output Output Sample Frame Signal Data Ready Acknowledge Output
Pin 3 4
I/O I O
Description Crystal Oscillator Input Crystal Oscillator Output
CLKR DATA FSR ACK
3
AT73C502 Differential-Ended ADC
Figure 4. QFP-44 package pin layout
XI XO N/C CLK N/C CLKR N/C ACK FSR DATA RESET
Analog Signals VINP3
Pin 18 19 20 21 22 23 24 25 7 9
I/O I I I I I I I I I I
Description Input to Converter #3 (+) Input to Converter #3 (-) Input to Converter #4 (+) Input to Converter #4 (-) Input to Converter #5 (+) Input to Converter #5 (-) Input to Converter #6 (+) Input to Converter #6 (-) Input to Voltage Monitoring Block Must be left floating
BGD CS VCC VCC PFAIL AGND VCIN VREF IADJUST VSA VSA
44 1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
39
38
37
36
35
34 33 32 31 30 29 28 27 26 25 24
MODE GND PD VDA VDA VSA VSA
VINN3 IINP1 IINN1 IINP2 IINN2 IINP3
SINGLE IINN3 IINP3 IINN2
IINN3 VCIN IADJUST
13
14
15
16
17
18
19
20
21
23 22
VDA VDA
VINP1 VINP2 VINP3 IINP1 IINP2 VINN1 VINN2 VINN3 IINN1
Digital Control Signals BGD
Pin 1 2 31 33 35 26
I/O I I I I I I
Description By-pass Control for Reference Voltage Chip Select Input Power Down Control for A/D Modulators Mode Selection Control Reset Input, Active High Single / Differential selector. * Low: Differential * High or n/c: Single-ended
Power Supply Pins VDA VSA AGND VREF VCC GND Crystal Osc Signals XI XO Analog Signals VINP1 VINN1 VINP2 VINN2
Pin 12, 13, 29, 30 10, 11, 27, 28 6 8 3, 4 32
I/O PWR PWR PWR PWR PWR PWR
Description CS Analog Supply, Positive, +5V Analog Supply, Negative, 0V Analog Ground Reference Output Reference Voltage Output Digital Supply, Positive, +5V Digital Supply, Negative, 0V Status Flags PFAIL PD MODE RESET SINGLE
Pin 5
I/O O
Description Output of Voltage Monitoring Block
Pin 43 44
I/O I O
Description Crystal Oscillator Input Crystal Oscillator Output Output Bus Signals CLK
Pin 41 39 35 36 37
I/O O O O O O
Description Master Clock Output Serial Bus Clock Output Serial Data Output Output Sample Frame Signal Data Ready Acknowledge Output
Pin 14 15 16 17
I/O I I I I
Description Input to Converter #1 (+) Input to Converter #1 (-) Input to Converter #2 (+) Input to Converter #2 (-)
CLKR DATA FSR ACK
4
AT73C500
AT73C500
AT73C500 DSP
Figure 5. PLCC-44 package pin layout
GND SOUT1 SOUT0 IRQ0 / PFAIL GND GND CLK STROBE VCC ADDR2 ADDR1
6
GND
5
4
3
2
1
44
43
42
41
40 39 38 37 36 35 34 33 32 31 30 29
ADDR0
Microprocessor Bus B7 B6
XRES
Pin 23 22 21 19 18 10 9 8
I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description P Bus, Bit7 P Bus, Bit6 P Bus, Bit5 P Bus, Bit4 P Bus, Bit3 P Bus, Bit2 P Bus, Bit1 P Bus, Bit0
7 8 9 10 11 12 13 14 15 16 17 18
B3
B0
B1
BRDY
B2
RD/WR
B5 B4 B3 B2 B1 B0 AT73C501 / AT73C502 and EEPROM Interface SOUT0
GND
VCC
GND
GND
B12
SIN
B13
SCLK
B14
IRQ1 / ACK
GND
GND
B15
B11
19
B4
20
GND
21
B5
22
B6
23
B7
24
N/C
25
B8
26
B9
27
GND
28
B10
Power Supply Pins VCC
Pin 35, 42 1, 2, 6, 7, 11, 12,16, 20, 27, 30, 34
I/O PWR
Description Digital Supply, Positive, +5V
Pin 4
I/O O
Description Serial Output, used as a clock for EEPROM Serial Output, used as Chip Select (CS) for AT73C501 and as Data Input (DI) for EEPROM Serial Data Input, data from AT73C501 or from EEPROM Serial Clock Input, bit clock from AT73C501
GND
PWR
Digital Supply, Negative, 0V
SOUT1
5
O
Digital Inputs CLK XRES IRQ0
SIN Pin 44 38 3 I/O I I I Description Clock Input Reset Input, active low Interrupt Input, usually connected to PFAIL output of AT73C501 Interrupt Input, connected to ACK Output of AT73C501 Control Signals of P Bus and Status/Mode Bus STROBE BRDY Pin 17 15 14 13 29 28 26 25 I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Status/Mode Bus, Bit7 Status/Mode Bus, Bit6 Status/Mode Bus, Bit5 Status/Mode Bus, Bit4 Status/Mode Bus, Bit3 Status/Mode Bus, Bit2 Status/Mode Bus, Bit1 Status/Mode Bus, Bit0 RD/WR ADDR0 ADDR1 SCLK
33 32
I I
Pin 43 37 40
I/O O I O
Description Strobe Output Microprocessor ready for I/O, Active Low Address Output 1, used for P bus Address Output 0, used for Status/ Mode bus and for Impulse Outputs Read/Write Signal
IRQ1
31
I
Status/ Mode Bus B15 B14 B13 B12 B11 B10 B9 B8
39 36
O O
5
AT73C501 and AT73C502
The AT73C501 consists of six, 16-bit analog-to-digital converters. The converters are equipped with single-ended inputs. For differential ended applications, the AT73C502 chip is used. The converters contain a reference voltage generator, voltage monitoring block and serial output interface. Both converters are based on high-performance, oversampling Sigma-Delta modulators and digital decimation filters.
Figure 6. Block diagram of the single-ended ADC chip, AT73C501
VOLTAGE MONITORING
SIGMA-DELTA MODULATOR SIGMA-DELTA MODULATOR SIGMA-DELTA MODULATOR SIGMA-DELTA MODULATOR SIGMA-DELTA MODULATOR SIGMA-DELTA MODULATOR
DECIMATION FILTER DECIMATION FILTER DECIMATION FILTER DECIMATION FILTER DECIMATION FILTER DECIMATION FILTER
SERIAL OUTPUT LOGIC
VOLTAGE REFERENCE
TIMING AND CONTROL
In a 50 Hz meter, the nominal decimated sampling rate of 3200 Hz is used. This corresponds to 64 samples per each line frequency cycle. 60 Hz meters operate with 3840 Hz sample rate. The master clock frequency of the ADC is 1024 times higher than the above frequencies, i.e. 3.2768 MHz in 50 Hz meters and 3.93216 MHz in 60 Hz systems. The default meter constant of AT73C500 energy counters is based on the above sample rates. Other sample frequencies can be used, but the energy results have to be scaled accordingly. If higher sampling rate is selected, the meter constant will also be increased by the same ratio. The three current inputs of AT73C501 are fed from secondary outputs of current transformers, from Hall sensors or other similar sensors. In differential-ended applications, such as with current shunt resistors, the AT73C502 ADC can be used. On any of these converters, the voltage inputs must be equipped with simple external voltage dividers. The input voltage range of each converter is 2V PP . The characteristics of a Watt-hour meter operating, according to IEC1036 specification, are based on a certain basic current, I B . As a default, the basic current of AT73C500 chipset is to 6.25% of the current input full scale value. This means that if a meter is designed for IB = 5A RMS, the full scale range of the current channels will be:
100 IFS = 5 A RMS x ---------- = 80 A RMS 6.25
The following current transformer and voltage divider configuration is recommended for a 230V, 3-phase system, with 5A basic current:
Voltage Inputs Converter full-scale input Corresponding full-scale line voltage / current 2.0VPP 270VRMS Current Inputs 2.0VPP 80ARMS
With the above settings, the nominal pulse rate of the meter constant outputs is 1250 impulses/kWh (1250 impulses/kVArh) and the rate of four display outputs 100 impulses/kWh (100 imp/kVArh). When used in a 5A transformer operated meter, the maximum current range can be scaled down to 8A for example. In this case, the meter constant will be ten times higher than in an 80A meter, i.e. 12500 impulses/kWh. Similarly, the starting current level will be transferred 2mA from 20mA.
6
AT73C500
AT73C500
If the nominal voltage is chosen to be 120V, the voltage divider can either have the same configuration as in the 230V meter, or it can be modified to produce 2.0Vpp with 140V phase voltage. In the latter case, the default meter constant will be roughly twice the constant of 230V meter, i.e. 2411 impulses/kWh. The meter constant can be scaled to an even number value by means of calibration. As described above, the configuration of voltage dividers and current transformers affects to almost all parameters being metered, like energy counters and impulse outputs. A calibration coefficient is provided for the adjustment of the display pulse rates. With this coefficient, the effect of various voltage divider and current transformer configurations can be compensated. Care should be taken that the dynamic range of the A/D converters is always effectively utilized. The use of calibration coefficients is described in the next section. Current and voltage samples of AT73C501/AT73C502 are multiplexed and transferred to AT73C500 through a serial interface. The timing of the interface is presented in the next section. AT73C501/AT73C502 contain an internal bandgap voltage reference. When used in class 0.5 and 0.2 meters, smaller temperature drift is required. This can be achieved by bypassing the internal reference and using temperature Figure 7. Block diagram of DSP software
FREQUENCY MEASUREMENT
compensated external reference instead. The reference is selected with the BGD input.
BGD 0 (VSS) 1 (VDD) Reference Internal External
There is an integrated voltage monitoring block on the converter chip. The PFAIL output is forced high if the level of voltage supplied to VCIN input drops below 4.2V. There is a hysteresis in the monitoring function and PFAIL returns low if voltage at VCIN is raised back above 4.3V. PFAIL output of AT73C501/AT73C502 can be connected to an interrupt input of AT73C500. AT73C500 detects the rising edge of PFAIL. To assure reliable power-down procedure after voltage break, the V CC supply of AT73C500 must be equipped with a 470 F or larger capacitor.
AT73C500
AT73C500 performs power and energy calculations. It also controls the interfacing to the AT73C501 (or AT73C502) and to an external microprocessor. The block diagram of the DSP is presented below.
f
CURRENT DERIVATION
u1(n) u2(n) u3(n) i1(n) i2(n) i3(n)
DC OFFSET SUPPRESSION PHASE CALIBRATION HILBERT TRANSFORM REACTIVE POWER MEASUREMENT GAIN AND OFFSET CALIBRATION VOLTAGE MEASUREMENT GAIN CALIBRATION
I U
ACTIVE ENERGY CALCULATION ACTIVE POWER MEASUREMENT GAIN AND OFFSET CALIBRATION APPARENT POWER EVALUATION POWER FACTOR DERIVATION
W P PF Q
REACTIVE ENERGY CALCULATION
Wq
Serial Bus Interface
The timing of the serial bus interface connecting the ADC and DSP devices is presented in Figure 5. The same bus is used to read the calibration data from an external EEPROM. This operation is described in section "Loading of Calibration Coefficients" on page 19. When the three current and three voltage samples are ready, AT73C501/AT73C502 raises the ACK output. AT73C500 detects the rising edge of ACK, and, after a few clock cycles, it is ready to read the samples through the serial bus. The transfer is initiated by CS/SOUT1 signal and the data bits are strobed in at the falling edge of CLKR/SCLK clock. Six 16-bit samples is transferred in the following sequence: I1, U1, I2, U2, I3 and U3.
7
Figure 8. Serial bus timing
CLK CLKR ACK FSR
CS 6 * 16 BITS DATA
CH1, B15 MSB CH1, B14 CH1, B0 LSB CH2, B15 MSB CH2, B0 LSB CH6, B1 CH6, B0
Operating Modes of AT73C500
The AT73C500 chipset has six operating modes. The mode is selected by three mode control inputs which AT73C500 reads through a bus during the initialization procedure after a reset state. The operation of AT73C501/AT73C502 is independent of the mode selected.
Mode Number 0 1 2 3 4 5 6 7 Mode Bit 2 0 0 0 0 1 1 1 1 Mode Bit 1 0 0 1 1 0 0 1 1
In operating mode 7, the default display pulse rate is 10 impulses per kWh, instead of 100 impulses per kWh, as in other modes.
Mode Bit 0 0 1 0 1 0 1 0 1
Operating Mode Not in use Normal operation Multi-channel operation Normal operation Multi-channel operation Test mode Not in use Normal operation
Calibration Data Storage
EEPROM EEPROM Micro-processor Micro-processor None
EEPROM
Normal Measurement Mode
AT73C500 devices support both stand-alone and microprocessor configuration. The calibration coefficients can either be supplied by a processor or stored in an 128 x 8-bit EEPROM. The ROM is interfaced with AT73C500 via three pin serial bus. AT73C500 and the processor communicate through an 8-bit bus. The only operational difference between stand-alone and P mode is the way of reading calibration coefficients. This allows various combinations of these two configurations to be utilized. For example, the calibration data can be stored in an EEPROM even though the processor reads and displays the measurement results supplied by AT73C500 device. In most cases, the use of external EEPROM gives flexibility to the meter testing and calibration, and also makes the processor interface easier to implement. Therefore, this configuration is recommended even in meters equipped with a separate microprocessor. The same sequence of basic calculations is performed both in poly-phase and single-phase meters. This sequence consists of DC offset suppression, phase, gain and offset calibration, calculations of measurement quantities and data transfer to P bus and pulse outputs. AT73C500 constantly monitors various tampering and fault situations, which are indicated by status bits. After a reset state, AT73C500 goes through an initialization sequence. The device reads the operating mode and fetches the calibration coefficients and adjustment factors for output pulse rate and starting current level, either from a non-volatile memory or from a microprocessor. After that the normal measurement starts. The reset state is normally activated by power-up reset following the recovery from a voltage interruption.
8
AT73C500
AT73C500
Measurements and Calculations The first operation performed by AT73C500 is digital highpass filtering. The purpose of the filtering is to remove the DC offset of both current and voltage samples. From offset free samples, active power is calculated phase-by-phase with simple multiplication and addition operations. First, the current samples are multiplied by voltage samples. The multiplication results are summed over one line period and finally the sum value is divided by 64. This discrete time operation gives the average power of one 50/60Hz period and the result corresponds to the following continuous time formula:
T 1 P= -- x [ A N x U N x sin { n x wt } x A N x I N x sin { n x wt + N } dt ] T n = 0 0 N
Measurement Registers For the measurement parameters 25 registers are allocated:
Register REG0 REG1 REG2 REG3 REG4 REG5 REG6 REG7 REG8 REG9 Meaning Phase 1, active power, P1(10T), 32-bit register; Phase 2, active power, P2(10T), 32-bit register; Phase 3, active power, P3(10T), 32-bit register; Phase 1, reactive power, Q1(10T), 32-bit register; Phase 2, reactive power, Q2(10T), 32-bit register; Phase 3, reactive power, Q3(10T), 32-bit register; Phase 1, apparent power, S1(10T), 16-bit register; Phase 2, apparent power, S2(10T), 16-bit register; Phase 3, apparent power, S3(10T), 16-bit register; Phase 1, power factor, PF1, 16-bit register; Phase 2, power factor, PF2, 16-bit register; Phase 3, power factor, PF3, 16-bit register; Active exported energy since the latest reset, +Wp, 32-bit counter; Active imported energy since the latest reset, -Wp, 32-bit counter; Reactive energy, inductive load, Wqind, 32-bit counter; Reactive energy, capacitive load, Wqcap, 32-bit counter; Number of 10T periods elapsed since the latest reset, 32-bit counter; Frequency, f, 16-bit register; Reserved for further use, 16-bit register; Phase 1, voltage U1, 16-bit register; Phase 2, voltage U2, 16-bit register; Phase 3, voltage U3, 16-bit register; Phase 1, current I1, 16-bit register; Phase 2, current I2, 16-bit register; Phase 3, current I3, 16-bit register.
N
=
--- x An x An x Un x In x cos ( n ) 2
1
n=0
REG10 REG11 REG12 REG13 REG14 REG15 REG16 REG17 REG18 REG19 REG20 REG21 REG22 REG23 REG24
where T = 1/50 Hz or 1/60 Hz, n = 1, 2, 3,..., 20 (basic 50/60 Hz frequency and the harmonics), An = frequency response of calculations. The total power is calculated by summing the power of each line phase. Reactive power calculation is based on a similar procedure. Before multiplying the current and voltage samples AT73C500 performs a frequency independent -90 degree phase shift of the voltage signal. This is realized with a digital Hilbert transformation filter. The bandwidth of reactive power measurement is limited to 360 Hz. Based on the active and reactive results apparent power and power factors are determined. RMS phase voltages are calculated by squaring and summing the voltage samples and finally taking a square root of the results. Current is determined by dividing apparent power result by corresponding phase voltage. Frequency measurement is based on a comparison of the line frequency and AT73C500 sampling clock frequency. The measurement range is from 20 Hz to 350 Hz. All measurements and calculations, except frequency measurement, are made over 10 line cycle periods. The results are updated and transferred to processor bus once in 200 ms.
The size of the registers is either 16-bit or 32-bit. IEC specifications apply to the calculations of active and reactive power and energy (REG 0-5 and REG 12-15). Other results are intended mainly for demand recording and for various diagnostic and display functions. The accuracy of those are limited due to the finite resolution.
9
In multi-channel mode the active exported energy of each three meters (phases) is stored in registers 12-14. REG15 is not in use. The maximum value of different power registers differs, depending on the calculation formulas used. The scaling of registers is described below. If a full scale sine signal is applied to voltage and current inputs and the voltage and current channels are exactly in the same phase, a value of 258F C2F7H will be produced in the 32-bit P1, P2 and P3 registers. The LS bit will correspond to about 34 microwatts in nominal input conditions of 270V maximum phase voltage and 80A maximum current. If the load is fully reactive ( 90 phase difference) and full scale signals are applied, the Q1, Q2 and Q3 register content will be 2231 594DH positive or negative, and the LSB will represent about 38 VAr. The maximum value of the 16-bit S registers is 258EH and this value is obtained if a full scale amplitude is produced to the current and voltage inputs. LS bit of the S registers correspond to about 2.25VA power. The following formula is used to calculate the power factor: abs ( P ) PF = sign ( Q ) x ----------------abs ( S ) The PF register contents 7FFFH represents power factor value one and the contents 0000H value zero. Negative PF values are stored correspondingly as negative binary numbers. It should be noted that the sign of power factor result indicates whether the loading is inductive (+) or capacitive (-). The contents of frequency register (REG17) actually represents a 16-bit figure which corresponds to the duration of 50 line frequency cycles. The measurement is made by comparing the line frequency with one of the sampling clocks of AT73C500 and therefore the result depends on the crystal frequency used. With default 3.2768 MHz crystal, the resolution of time value is 1.25 ms. To get the frequency, the following calculation has to be made: 40000 -Hz f = -----------------REG17 If the master clock frequency (MCLK) of AT73C500 is not nominal, the following formula gives frequency results: 40000 MCLK f = ------------------ x ----------------------------- Hz REG17 3.2768MHz
In the default condition, value 7FFFH of register 17 corresponds to 1.22 Hz frequency, value 0320H represents 50Hz and 0001H 40 kHz. However, in practice, the bandwidth of frequency measurement is limited to 20 Hz to 350 Hz. The frequency measurement is locked with one of the phase voltages. If this voltage disappears, AT73C500 tries to track one of the other phases. The frequency measurement works down to about 10% level of the full scale voltage range. The harmonics content of phase voltage should be below 10%. If it is higher, erroneous frequency results may be obtained. The voltage registers (REG19-REG21) are scaled so that full scale sinusoidal input signal at AT73C501/AT73C502 voltage channels will produce 7A8BH value into voltage registers. This means that the resolution of the registers is about 8.6 mV. Accordingly, full scale current will produce 7DA4H to current registers (REG22-REG24) providing a resolution of about 2.5 mA. In practice, the voltage can be measured down to about 25V level and current down to about 100mA. If either voltage or current, or both, contain a considerable amount of harmonics producing a square wave type waveform, it is recommended to scale the input range so that the maximum peak-to-peak value is at least 10% below the full scale range of inputs. This is to avoid overflow in the calculations performed by AT73C500. Energy Counters Four 32-bit counters (REG12-REG15) measure energy consumption. In nominal situations, the counters are always incremented when 0.4Wh (0.4VArh) energy is consumed. The counters can store minimum of 1100 days consumption, provided that AT73C501/AT73C502 and AT73C500 are used with default settings. Impulse outputs are generated from these counters. The meter constant rate represents 2 LSBs of a counter which equals 0.8 Wh (0.8 VArh) and produces 1250 impulses/kWh. (1250 impulses/kVArh). In modes 1 to 4, the display pulses are generated from 25 LSBs of a counter. This corresponds to an impulse rate of 100 impulses/kWh (100 impulses/kVArh). It is possible to adjust this rate with MCC calibration coefficient. In mode 7, 250 LSBs of the energy register is needed to generate one impulse (10 impulses/kWh). The default values above are based on 80ARMS full scale current, 270VRMS full scale voltage and 3.2768 MHz clock rate. The crystal frequency will affect the values of energy registers (REG12-REG15) and time register (REG 16). It will also change the pulse rates of the impulse outputs.
10
AT73C500
AT73C500
It is recommended that 50 Hz meters are operated from 3.2768MHz crystal. In 60 Hz system, a 3.93216 MHz clock is normally used. Because the clock frequency generates a time reference for energy calculations, the content of energy registers and also the pulse rate of impulse outputs will change when crystal is changed. For example, the nominal meter constant and display pulse rate of 60 Hz meter (3.93216 MHz clock) is: 60Hz imp imp MC = ------------- x 1250 ----------- = 1500 ----------50Hz kWh kWh and imp 60Hz imp DP = ------------- x 100 ----------- = 120 ----------kWh kWh 50Hz The LSB of energy registers correspond to 0.33Wh instead of 0.4Wh, as follows: 3.2768MHz E LSB = --------------------------------- x 0.4Wh = 0.333333...Wh 3.93216MHz The pulse rate can be scaled to 100 imp/kWh by programming value 5 to MCC coefficient, as below:
Wh 1 1 --------------- x IMP = (25 + MCC) -------- x E LSB = 30 imp 0.3333...Wh = 10 imp imp
which equals 100 impulses per kilowatt hour. The following table summarizes the contents of all measurement registers.
Register REG0 - REG2 REG3 - REG5 REG6 - REG8 REG9 - REG11 REG12 - REG15 REG16 REG17 REG19 - 21 REG22 - 24
Conditions U = 270V, I = 80A, PF = 1 U = 270V, I = 80A, PF = 0 U = 270V, I = 80A PF = 1 PF = -1 W = 1.718GWh
Full Scale Output (hex) 258F C2F7 2231 594D 258E 7FFF 8001 FFFF FFFF FFFF FFFF 7FFF 7A8B 7DA4
Resolution (hex) 34.276 W 37.653 VAr 2.2467 VA 0.0000305 -0.0000305 0.4Wh 0.2s 1.25 ms 8.6 mV 2.5 mA
T = 238609.3h
50*T = 40.959s U = 270V I = 80A
11
Output Operations The data output by AT73C500 can be divided into three categories: data to external processor, status information and impulse outputs. AT73C500 reads mode information, and in mode 3 and 4, also calibration data via external bus. For the I/O operation, two 8-bit buses are allocated. The same eight data lines are reserved both for the impulse outputs and for the processor interface. The separation is done with two address pins. When communicating with the microprocessor, address 1 (pin ADDR1) is activated (high). Impulses are output combined with a high level of address 0 (ADDR0). For status information separate 8-bit bus is reserved. The table below describes the use of the two buses of AT73C500.
Data bits B0 - B7 B8 - B15 B0 - B7 B12 - B14 Bus Data Bus Status Bus Data Bus Status Bus Address ADDR0 ADDR0 ADDR1 ADDRx Mode Output Output Input/ Output Input Usage Impulse Outputs Status Information Processor Interface Mode Inputs
PACKAGE 0 Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sync LS Sync MS Mode Status REG0 REG0 REG0 REG0 REG1 REG1 REG1 REG1 REG2 REG2 REG2 REG2 Order Single byte Single byte Single byte Single byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte (LS+1) byte (LS+2) byte MS byte PACKAGE 1 Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sync LS Sync MS Mode Status REG3 REG3 REG3 REG3 REG4 REG4 REG4 REG4 REG5 REG5 REG5 REG5 Order Single byte Single byte Single byte Single byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte (LS+1) byte (LS+2) byte MS byte Meaning Synchronization Synchronization Mode information Status information Reactive power, phase 1 Reactive power, phase 1 Reactive power, phase 1 Reactive power, phase 1 Reactive power, phase 2 Reactive power, phase 2 Reactive power, phase 2 Reactive power, phase 2 Reactive power, phase 3 Reactive power, phase 3 Reactive power, phase 3 Reactive power, phase 3 Meaning Synchronization Synchronization Mode information Status information Active power, phase 1 Active power, phase 1 Active power, phase 1 Active power, phase 1 Active power, phase 2 Active power, phase 2 Active power, phase 2 Active power, phase 2 Active power, phase 3 Active power, phase 3 Active power, phase 3 Active power, phase 3
For status and impulse outputs, external latches are needed to store the information while buses are used for other tasks. In most cases, the data bus of AT73C500 and processor I/O bus can be connected directly with each other. The data transfer is controlled by handshake signals, ADDR1, RD/WR, STROBE and BRDY. One of the status outputs DATRDY (B9, ADDR0) can be used as an interrupt signal. Interrupt can be also generated from the handshake lines. In most meters, only some of the I/O operations of AT73C500 are needed. If a meter contains a separate processor, status outputs of AT73C500 are typically not used since the processor will anyway track the status information supplied by AT73C500. Often only one or two of the impulse outputs are wired to the test LED or electromechanical counter. Data Transfer to External Microprocessor The calculation results of AT73C500 are transferred to processor via 8-bit parallel bus. During normal operation, the information transfer is divided into six packages which are written in 200ms intervals after the calculations over ten line frequency cycles have been completed. There is a time interval of one line cycle between each individual data package. The first four bytes of a package contain synchronization, mode and status information, and the rest 12 bytes are reserved for the actual measurement results. The contents of the six data packages are as follows:
12
AT73C500
AT73C500
PACKAGE 2 Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sync LS Sync MS Mode Status REG6 REG6 REG7 REG7 REG8 REG8 REG9 REG9 REG10 REG10 REG11 REG11 Order Single byte Single byte Single byte Single byte LS byte MS byte LS byte MS byte LS byte MS byte LS byte MS byte LS byte MS byte LS byte MS byte Meaning Synchronization Synchronization Mode information Status information Apparent power, phase 1 Apparent power, phase 1 Apparent power, phase 2 Apparent power, phase 2 Apparent power, phase 3 Apparent power, phase 3 Power factor, phase 1 Power factor, phase 1 Power factor, phase 2 Power factor, phase 2 Power factor, phase 3 Power factor, phase 3 15 16 REG14 REG14 (LS+2) byte MS byte 14 REG14 (LS+1) byte Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 Data Sync LS Sync MS Mode Status REG12 REG12 REG12 REG12 REG13 REG13 REG13 REG13 REG14 PACKAGE 3 Order Single byte Single byte Single byte Single byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte Meaning Synchronization Synchronization Mode information Status information Active exported energy Active exported energy Active exported energy Active exported energy Active imported energy Active imported energy Active imported energy Active imported energy Reactive energy, inductive load Reactive energy, inductive load Reactive energy, inductive load Reactive energy, inductive load
13
PACKAGE 4 Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sync LS Sync MS Mode Status REG15 REG15 REG15 REG15 REG16 REG16 REG16 REG16 REG17 REG17 REG18 REG18 Order Single byte Single byte Single byte Single byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte (LS+1) byte (LS+2) byte MS byte LS byte MS byte LS byte MS byte Meaning Synchronization Synchronization Mode information Status information Reactive energy, capacitive load Reactive energy, capacitive load Reactive energy, capacitive load Reactive energy, capacitive load Counter Counter Counter Counter Frequency Frequency Reserved Reserved Byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sync LS Sync MS Mode Status REG19 REG19 REG20 REG20 REG21 REG21 REG22 REG22 REG23 REG23 REG24 REG24
PACKAGE 5 Order Single byte Single byte Single byte Single byte LS byte MS byte LS byte MS byte LS byte MS byte LS byte MS byte LS byte MS byte LS byte MS byte Meaning Synchronization Synchronization Mode information Status information Voltage, phase 1 Voltage, phase 1 Voltage, phase 2 Voltage, phase 2 Voltage, phase 3 Voltage, phase 3 Current, phase 1 Current, phase 1 Current, phase 2 Current, phase 2 Current, phase 3 Current, phase 3
14
AT73C500
AT73C500
The six data packages arrive as follows: Figure 9. Data transfer to processor in six packages
20 ms 200ms = 655360 clocks @ 3.2768 MHz
Pack 0
DATRDY
Pack 1
Pack 2
Pack 3
Pack 4
Pack 5
Pack 0
Pack 1
Pack 2
Pack 3
LINE PERIOD
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
In normal mode, the Sync LS byte indicates the number of data package which will follow (value 0...5). There are also two special situations indicated by this byte. Value six of Sync LS byte means that the processor is expected to supply calibration data to AT73C500. Value seven is written by AT73C500 in case power interruption is detected and billing information needs to be transferred to microprocessor. In this case the processor knows that both packages 3 and 4 will follow one after each other as shown in Figure 10. Content of Sync LS byte is described in the following table. Bits 3-7 of the Sync LS byte are not used.
Sync LS byte B7 - B3 XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX B2 0 0 0 0 1 1 1 B1 0 0 1 1 0 0 1 B0 0 1 0 1 0 1 0 Data package 0 1 2 3 4 5 (none) Mode Normal operation, Data output Normal operation, Data output Normal operation, Data output Normal operation, Data output Normal operation, Data output Normal operation, Data output DSP waiting for calibration data PFAIL active, billing information to be transferred
The Sync MS byte contains a unique 8-bit data, 80H. It can be used as a synchronization byte by the external controller. The mode byte contains the following information: Figure 10. Meaning of bits in mode byte
Mode byte
B7
B6
B5
B4
B3
B2
B1
B0
Not used
State of MODE input pins of the DSP
The contents of the status byte equals the content of the external Status bus as described in the section "Status Information" on page 17. In the beginning of I/O operation, AT73C500 writes a high pulse to B9 pin of the Status bus (ADDR0). This pin can be externally latched to lengthen the pulse over the whole output operation. It can be used to generate a data ready (DATRDY) interrupt to processor. Figure 11 shows the timing of one data package. In nominal conditions, it takes 200 clock cycles to transfer all 16 bytes. A high pulse (DATRDY) is written to bit B9 (SMBUS1) of Status bus 11 clocks before the first byte is available and low pulse 12 clocks after the last byte has been sent.
XXXXX
1
1
1
3 and 4
15
Figure 11. Contents of a data package
200 clock cycles 45 clock cycles 143 clock cycles
LATCHED DATRDY CLK STROBE
Sync LS
Sync MS
Mode Status data
Status
Data 1
Data 2
Data 11
Data 12
Synchronisation data
Measurement data, 12 bytes
AT73C500 offers some time for the processor to analyze the synchronization, status and mode information before starting to supply the measurement results. The 12 measurement bytes are written on every 11th clock period. Four handshake signals are provided, ADDR1, RD/WR, STROBE and BRDY, for interfacing with the microprocessor. ADDR1 is always taken high when AT73C500 is either Figure 12. Handshake signals of the DSP
writing to P bus or reading the bus contents. When used with slow peripheral, the BRDY input of AT73C500 can be used to hold the device in write mode until the processor has finished reading the bus. However, the total length of one data package should always be less than 300 clock cycles of AT73C500. Longer I/O periods may result erroneous measurement results.
CLK
SDLY
DATA FROM DSP
DDLY
BRS
BRDY
SH
STROBE
ASU
ADDR1
RWSU RWH
RD/WR
Following the falling edge of BRDY, the data can be strobed into the P by the rising edge of the STROBE signal. If the microprocessor is able to read data continuously, BRDY can be kept constantly low. Also BRDY should be low whenever DATRDY is inactive allowing AT73C500 freely use its buses.
To avoid conflicts, the processor should always keep its bus in tri-state mode, unless it is used to write calibration coefficients to AT73C500.
16
AT73C500
AT73C500
Status Information AT73C500 provides the following status information through the Status bus of AT73C500 (B8 - B15, ADDR0).
Status Bus Bit B15 B14 B13 B12 B11 B10 B9 B8 Status Flag TAMP STUP L3 L2 L1 FAIL DATRDY INI Meaning High: Potential event of tampering detected High: Current of all phases below starting level High: Phase 1 voltage above 10% of full-scale High: Phase 2 voltage above 10% of full-scale High: Phase 3 voltage above 10% of full-scale High: Operating error detected High: Data available on the P bus Low: AT73C500 in initialization phase, EEPROM interface in use, AT73C501 (or AT73C502) interface disabled
High level of Lx flags indicates that a phase voltage is above 10% level of the full scale voltage. If a voltage drop is detected, the corresponding status bit is written low. AT73C500 is continuously monitoring the voltage of each phase.
FAIL flag signifies that something abnormal has been detected. The following situations may cause a high level of FAIL: read operation of calibration coefficients is not successful, the serial bus of AT73C501 or AT73C502 is not working properly, the measurement results can't be transferred to microprocessor, AT73C500 has detected an internal failure. If any of the calibration coefficients and corresponding back-up values do not match, AT73C500 performs two extra read operations to eliminate the possibility of a transfer error. If the error still exists after the third trial, incorrect coefficients are replaced by the default values. FAIL flag is activated indicating that a potential error has been detected. FAIL is also taken high in case it is not possible to read calibration coefficients from the P or EEPROM, or if the processor supplies too few coefficients. In both cases, the read operation will finish in a time-out situation. The voltage monitoring block of AT73C501/AT73C502 is used to detect voltage interruptions before the supply voltage of AT73C500 drops. High level of PFAIL output at the ADC indicates a voltage break situation. The measurement results supplied by AT73C501/AT73C502 may be erroneous, and AT73C500 and microprocessor has to be prepared for supply voltage interruption. A high level of PFAIL causes an immediate write of data packages 3 and 4 (accumulated energy information) to processor bus. The timing of this operation is presented in Figure 13. There are 16 clocks between the two 12 byte data packages but the header bytes are not repeated in the beginning of package 4.
Figure 13. Transfer of billing information to processor following a PFAIL interrupt
337 clock cycles 45 clock cycles 280 clock cycles
LATCHED DATDRY CLK STROBE
Sync LS Sync MS Mode Status Data 1 Data 2 Data 12 Data 1 Data 2 Data 12
Synchronisation data
Status data
Measurement data, 12 bytes + 12 bytes
In case of an imminent voltage break, the microprocessor stores the energy values into a non-volatile memory. The devices can operate for a short period of time powered by an electrolytic capacitor or by battery back-up. AT73C500 devices are taken to a soft reset state and normal operation will be recovered after the supply voltage is high again. About one line cycle is needed to start normal measurements. During this initialization phase no calculations are performed.
STUP output (active high) indicates that the current of each of the three phases is below the specified starting level and no energy is accumulated. This status flag is very useful during the calibration of a meter since immediate feedback about staring current level is provided. TAMP flag informs about potential tampering. It is activated if one or more phase currents are zero or negative. Therefore it very effectively indicates current transformer reversal or short-circuit.
17
Impulse Outputs AT73C500 provides eight impulse outputs, four meter constant outputs and four pulse outputs to drive electromechanical display counters which can register exported and imported active energy and capacitive and inductive reactive energy. These outputs use the same output lines as used for the processor interface. Impulses are combined with address 0 (ADDR0). The table below shows the impulse outputs available in modes 1 and 3. Mode 7 offers the same outputs, but the rate of the display pulses is 10imp/kWh (kVArh).
Impulse Outputs in Operating Modes 1 and 3 Output Bit B7 B6 B5 B4 B3 B2 B1 B0 Impulse - VArh + VArh - Wh + Wh + Wh - Wh + VArh - VArh Output Type Meter Constant Meter Constant Meter Constant Meter Constant Display Display Display Display Impulse Rate 1250imp/kVArh 1250imp/kVArh 1250imp/kWh 1250imp/kWh 100imp/kWh 100imp/kWh 100imp/kVArh 100imp/kVArh
active energy of the three single phase channels summed together as shown in the table below.
Output Bit B7 B6 B5 B4 Impulse Not Used Not Used Not Used Wh Wh Wh Wh Not Used Output Type Not Used Not Used Not Used Meter Constant Sum of all 3 channels Display, Channel 1 Display, Channel 3 Display, Channel 2 Not Used Impulse Rate 1250imp/kWh
B3 B2 B1 B0
100imp/kWh 100imp/kWh 100imp/kVArh -
Test Mode
This mode can be used for initial calibration purposes or in a special meter for additional processing of sample data. In this mode, AT73C501/AT73C502 samples the six inputs normally and transfers the samples to AT73C500, which performs DC suppression and further writes the samples to 8-bit processor bus together with header bytes in the following sequence.
Byte 1 2 3 4 5 6 7 8 9 10 Contents Sync LS byte Sync MS byte Mode Byte Status Byte I1, LS byte and MS byte U1, LS byte and MS byte I2, LS byte and MS byte U2, LS byte and MS byte I3, LS byte and MS byte U3, LS byte and MS byte
An external register is needed to latch and buffer the pulses. The register can further drive both electromechanical display counters and LEDs. In modes 1 to 4, the nominal pulse rate of display outputs is 100imp/kWh or 100imp/kVArh (UMAX = 270V, IMAX = 80A) and meter constant outputs 1250imp/kWh (1250imp/kVArh). The length of each display pulse is 117ms when operated from 3.2678 MHz crystal. Meter constant pulse stays high for 20 ms. If the devices are used in a 5A meter, current inputs can be scaled to 8A full scale level. In this case, the nominal impulse rates are ten times higher than the above values.
Multi-channel Mode
Modes 2 and 4 are reserved for multi-channel operation. In these modes, the chips operate like three independent single phase meters and store the calculation results in separate registers phase-by-phase (meter-by-meter). The basic sequence of operation is otherwise similar to the normal mode. Impulse Outputs In multichannel operation, three impulse outputs are available for display counters. The absolute energy value is measured and the reversal of current flow doesn't affect to pulse rates. Meter constant pulse rate corresponds to total
Several input combinations can be measured to check the gain and phase error in different conditions. An interfacing computer can be programmed to calculate the calibration coefficients based on the samples supplied by AT73C500. At the end of the calibration, the coefficients have to be stored in a non-volatile memory of the meter as described in "Loading of Calibration Coefficients" on page 19.
18
AT73C500
AT73C500
Calibration
The calibration coefficients always have to be loaded into AT73C500 registers after reset state. The coefficients are either read from an external EEPROM or supplied by a microprocessor via the 8-bit bus. Loading of Calibration Coefficients In modes 3 and 4, a microprocessor takes care that the coefficients are kept in a non-volatile memory during voltage break. After the voltage break, the DSP first writes the Figure 14. Timing of calibration coefficient read operation four header bytes, Sync LS, Sync MS, mode and status information on the P bus and then starts waiting for the calibration data. The processor reads the status and mode and after that writes the coefficients on the bus. The contents of AT73C500 header bytes is described in "Data Transfer to External Microprocessor" on page 12 and "Status Information" on page 17.
CLK
DATRDY
FT500 READY TO READ CALIBRATION DATA
STROBE
SYNC LS SYNC MS MODE STATUS
...
COEFFICIENT 0
COEFFICIENT 42 COEFFICIENT 1 COEFFICIENT 43
HEADER DATA SUPPLIED BY FT500D
44 COEFFEICIENTS READ
Before using the P bus, AT73C500 writes a short pulse (DATRDY) to B9 bit of the Status bus combined with high level of address 0 (ADDR0 output). This bit can be taken directly or through an external latch to the interrupt input of the processor. After writing the status and mode bytes, AT73C500 goes to a read mode and starts waiting for calibration coefficients from the P. Processor supplies the coefficients as 8-bit bytes one after another. The timing of this sequence is presented in Figure 14.
Nine gain calibration, six offset calibration and three phase calibration coefficients are read into the AT73C500 memory. At the same time, a scaling factor for the display pulse rate and an adjustment value for starting current is stored. To minimize the risk of erroneous calibration values, a back-up value of each coefficient is also transferred by the microprocessor or from the ROM. The back-up value has to be written as 2's complement binary number of the actual calibration figure.
19
The calibration data is transferred in the following sequence:
Byte 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 Calibration Coefficient PC1 PC2 PC3 MCC Not used AGC1 AGC2 AGC3 RGC1 RGC2 RGC3 UGC1 UGC2 UGC3 STUPC AOF1 AOF2 AOF3 ROF1 ROF2 ROF3 OFFMOD Byte 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Calibration Coefficient PC1 back-up PC2 back-up PC3 back-up MCC back-up Not used AGC1 back-up AGC2 back-up AGC3 back-up RGC1 back-up RGC2 back-up RGC3 back-up UGC1 back-up UGC2 back-up UGC3 back-up STUPC back-up AOF1 back-up AOF2 back-up AOF3 back-up ROF1 back-up ROF2 back-up ROF3 back-up OFFMOD back-up
The meaning of the calibration coefficient mnemonics are as follows:
Mnemonic PCN MCC AGCN RGCN UGCN STUPC AOFN ROFN OFFMOD Meaning Phase calibration factor, phase N Display pulse adjustment factor for active and reactive energy Gain calibration factor for active power and energy calculation, phase N Gain calibration factor for reactive power and energy calculation, phase N Gain calibration factor for phase voltage, phase N Starting current adjustment factor Offset calibration factor for active power and energy calculation, phase N Offset calibration factor for reactive power and energy calculation, phase N Controls the use of offset factors
20
AT73C500
AT73C500
AT73C500 provides four handshaking signals, ADDR1, RD/WR, STROBE and BRDY, for interfacing with the microprocessor. Microprocessor can use the BRDY input of AT73C500 to extend the read and write cycles. AT73C500 stays in the read or write mode as long as BRDY is high. BRDY is sampled at the rising edge of AT73C500 master clock. As soon as BRDY goes low, the read/write cycle of AT73C500 will end at the first rising edge of CLK clock. During read operation data is latched into AT73C500 register on the rising edge of the STROBE signal following the low level of BRDY. A more detailed description about the handshake signals is presented in section "Data Transfer to External Microprocessor" on page 12. Fifteen idle cycles are inserted by AT73C500 between the read operation of each calibration byte. This allows the processor to prepare the next coefficient for transfer or to raise the BRDY signal in case it is not ready to write the following byte. If the data is available, BRDY can be kept constantly low. Microprocessor has to always supply all 44 calibration bytes even though some of those may be zero and don't affect to measurement results. If AT73C500 detects an error when comparing the calibration data and corresponding back-up values, it writes the DATRDY bit high and after that the header bytes on processor bus indicating that it is still in initialization routine and wishes to get the calibration data to be transported once again. If the error still exists after the third trial, AT73C500 notifies the situation by a FAIL status bit and starts normal operation, discarding potentially incorrect calibration coefficients. If AT73C500 is programmed to mode 1 or 2, the coefficients are stored in an EEPROM of type AT93C46. The ROM has to support communication through a three pin serial I/O port. The serial ROM interface uses the same port, which also connects AT73C500 to AT73C501/AT73C502 sample output. During the initialization phase, the ADC interface has to be disabled. This can be done by B8 bit of AT73C500 Status bus (ADDR0). The output has to be latched by an external flip-flop to keep the state over the whole initialization period. The same output can be used as Chip Select input for the EEPROM. AT73C500 reads, checks and stores automatically all 44 calibration coefficients. After that, B8 bit of Status byte is written low and normal measurement can start. If the EEPROM contains erroneous data and one or more coefficients don't match with their back-up values, the same procedure is followed as in the processor mode. Gain Calibration Gain calibration is used to compensate the accumulated magnitude error of voltage dividers, current transformers and A/D converters. There is a separate 8-bit gain calibration coefficient for each phase, and for active and reactive energy measurement. A similar formula is also used to calibrate the phase voltage values, only the calibration range is different, 20% for power and 8% for voltage. These calibrations will automatically correct the gain error of other measurement parameters. The following calculations are done to get the calibrated results. For active power: AGC N P N = P N x 1 + 0.2 x --------------- 128 where PN is the active power of phase N and AGCN is the gain calibration factor of that phase. The valid range for AGCN is -128 to +127. Similarly, for reactive power: RGC N Q N = Q N x 1 + 0.2 x ---------------- 128 where QN is the reactive power of phase N and RGC N is the gain calibration coefficient for that phase. RGCN valid range is -128 to +127. Gain calibration performed on voltage measurements are: UGC N U N = U N x 1 + 0.08 x ---------------- 128 where UN is the line voltage of phase N and UGCN is the corresponding gain calibration coefficient, ranging from -128 to +127. Apparent power and current are automatically gain adjusted to match the calibrated settings of active power, reactive power and voltage. Offset Calibration The low current response of current sensors is often more or less non-linear. The error caused by this non-linearity can be compensated by a small offset factor which is added in power results. Offset calibration is done for active and reactive power, separately for each phase. The following formulas are used: AOF N P N P N + --------------- x 0.004157 x sign (P N ) x P FS 128 and ROF N Q N = Q N + --------------- x 0.00457 x sign(Q N ) x Q FS 128
where P N and Q N are the active and reactive power for phase N, AOFN and ROFN are the respective offset calibration coefficients and PFS and QFS are the corresponding full
21
scale values of the powers. The nominal full-scale values are: P FS = 270V x 80A = 21.6kW Q FS = 270V x 80A = 21.6VAr The valid range for the offset calibration factors is -128 to +127. The scale of offset calibration for active and reactive power is different, 89W versus 98VAr in nominal conditions of 270V maximum phase voltage and 80A maximum phase current. Typically, a small offset factor of a few watts is enough to compensate the non-linearity of current sensing. It should be noted that offset calibration will also affect the starting current level of a meter. If the full scale current or voltage is changed to a non-default value, the range for offset calibration will be scaled accordingly. The same offset value is used independent of phase angle. However, as default (OFFMOD=0), the sign of power is taken into account in the calculations so that positive offset factor will always increase the absolute power value and negative coefficient will decrease absolute results. This guarantees that current sensor non-linearity is corrected in the same way even though the current flow is reversed. It is possible to change this default condition by programming value one to OFFMOD coefficient. In this case, offset coefficient will be always added to power result without checking the sign of the power. Positive coefficient will increase the absolute value of positive power results and decrease the absolute value of negative result. Phase Calibration The phase difference between voltage and current channel is compensated with three 8-bit phase calibration figures. The displacement is usually due to the phase shift in current transformers. Based on the calibration values, the DSP interpolates new current samples with sample instants coinciding with the corresponding voltage samples. The following formula is used to determine the phase offset to be used in the interpolation. One 8-bit phase calibration value is stored for each of the three phases. PC N PO N = ----------- x 5.625 128 where PON is the sample phase offset of channel N, measured as phase(U) - phase (I). The allowed range for phase calibration factor, PCN, is -128 to +127. Starting Current Adjustment The meter IC is designed to fulfill IEC 1036, class 1 specification. This specification is based on a certain basic current, Ib . As a default, AT73C500 operates with 5A basic
current. The chip set has a preprogrammed starting current level of 1 I SU = ------------ x I FS 4000 where IFS is the full scale current of the meter, i.e. 80A in nominal conditions. The default startup current corresponds to 0.4% of the 5A Ib, assuming that the full-scale range is 80A. When the phase current is below the starting level, the calculated cycle power results are replaced by zeros and no energy is accumulated. It is possible to adjust the start-up level in the range of 0.2 to 10 compared with the nominal value. This is performed with a special calibration factor. The following formula is used to determine the current: 1 I SU = ------------ x I FS x (1 + 0.2 x STUPC) 4000 where STUPC is the starting current calibration factor, allowed to vary in range -4 to +45, only. Care should be taken that the STUPC is correctly programmed and is not beyond -4 to 45 range. Also, it should be noted that low starting thresholds may force the device to a level where accuracy is restricted due to a finite resolution of converters and mathematics. Adjustment of Display Pulse Rate An 8-bit byte is provided for adjustment of the impulse rate of display pulses. This coefficient will only affect the display pulse rate of active and reactive energy but not to the meter constant rate. The content of all measurement registers will remain unchanged. The impulse rate can be scaled in the range of 1 to 10 compared to the nominal value. In default conditions (Umax = 270V, Imax = 80A) the LSB of energy registers REG12-15 (See "Status Information" on page 17.) corresponds to 0.4Wh. This means that accumulated 25 LSBs of energy will generate one pulse to the display pulse output (25 x 0.4Wh/impulse = 10 Wh/impulse = 100 impulses/kWh). By using MCC calibration coefficient, the nominal figure 25 can be changed in the range of 25 to 250. The following formulas are used to calculate the impulse rate. IMP = (25 + MCC) x E LSB and 1000 PR = ------------------------------------------------(25 + MCC) x E LSB where ELSB is the energy value of one LSB in the energy register, 0.4Wh in default conditions. When the meter is
22
AT73C500
AT73C500
operated in non-standard conditions, the energy LSB may be recalculated as: U FS x I FS 3.2768MHz E LSB = ----------------------------- x ------------------------------ x 0.4Wh 270V x 80A f where f is the clock frequency used, and UFS and IFS are the full-scale values of voltage and current. In case the meter is used with a non-default voltage divider or current sensor, MCC factor is a convenient way to readjust the impulse rate. Example The meter is to be configured for use in 120V networks, with a maximum line voltage of 140V. The display pulse rate is required to remain at 100imp/kWh. To start off, the front end of the meter must be configured for the new line voltage. The voltage dividers must be configured to produce an input signal of 0.707V at the input of the ADC at maximum line voltage. At nominal meter settings, the voltage divider ratio is 270V:0.707V, in this case it must be 140V:0.707V. Note that adjusting the line voltage of the meter will render the formatting of most calculation registers to alternative settings. For example, the meter constant pulse rate will change as follows: 270V x 80A f imp MC = ------------------------------ x ----------------------------- x 1250 ----------U FS x I FS 3.2768MHz kWh In our case of a meter for 120V networks, the new meter constant pulse rate would be: imp imp 270V MC = ------------- x 1250 ----------- = 2410.714... ----------kWh kWh 140V To make the meter constant pulse rate to an even number, say 2500, we may choose to either re-scale the line voltage or scale the maximum line current. 2500 impulses per kilowatt hour is gained by either setting the maximum line voltage to: 270V imp U FS = ------------------------- x 1250 ----------- = 135V imp kWh 2500 ----------kWh or by retaining the line voltage at 140V and scaling the maximum line current to: 270V x 80A imp I FS = --------------------------------------------- x 1250 ----------- = 77.143...A imp kWh 140V x 2500 ----------kWh Regardless of which parameter (or both) is chosen, the scaling process is a simple matter of gain calibration. If, for 23 example, the line voltage is chosen to be rescaled to 135V, this is realized with a resistor divider of half the nominal, and finetuning using the voltage gain coefficients. Also, all values resulting from voltage calculation, such as the data transferred via energy registers, should be normalized with respect to the new voltage setting. Going back to the calibration of the display pulse rate, the new LSB value of energy registers is: 140V E LSB = ------------- x 0.4Wh = 0.20741...Wh 270V To maintain the display pulse rate at 100, the MCC calibration coefficient must be programmed as:
1000 1000 MCC = ----------------------------- - 25 = ---------------------------------------------------------- - 25 = 23.216... 23 PR x E imp LSB 100 ----------- x 0.20741Wh kWh
The energy value of each display counter impulse is thereafter: 1 140V Wh IMP = (25 + 23) -------- x ------------- x 0.4Wh 10.0 -------imp 270V imp
In mode 7, the default display pulse rate is 10 impulses/kWh(kVArh) instead of 100 impulses/kWh. This is convenient for meters where only one decimal digit wants to be shown. This default rate can also calibrated and the calibration formulas are: IMP = (250 + MCC) x E LSB and 1000 PR = ---------------------------------------------------(250 + MCC) x E LSB
Master Clock
The master clock of AT73C500 is generated by a crystal oscillator with crystal connected between pins XI and XO of AT73C501/AT73C502. Master clock can also be fed to the XI input from a separate clock source. The system clock rate of AT73C500 is the same as the clock of AT73C501/AT73C502 and is fed to the CLK input of the device from the CLK output of AT73C501/AT73C502.
Electrical Characteristics
Absolute Maximum Ratings
Parameter Supply Voltage VCC, VDA, VDDA Input Voltage, Digital Input Voltage, Analog Input Voltage, CI and VI inputs Ambient Operating Temp. Storage Temperature Min 4.75 -0.3 -0.3 1.25 -25 -65 Typ Max 5.25 VDD +0.3 VDA +0.3 3.75 +70 +150 Unit V V V V C C
Measurement Accuracy
The accuracy measurements are based on the usage of the AT73C500 DSP with the single-ended ADC, AT73C501. Using the differential-ended ADC, AT73C502, improves some of the results. Input Conditions When specifying measurement accuracy, it is assumed that 80ARMS phase current will produce 2VPP full scale input voltage to current converters. The basic current, IB, is supposed to be 5ARMS. The nominal phase voltage, UN, is specified to be 230VRMS and 2VPP full scale input is produced by 270VRMS. Overall Accuracy, Active and Reactive Power and Energy Measurement Overall accuracy including errors caused by A/D-conversion of current and voltage signals, calibration and calculations. The accuracy figures are measured in nominal conditions unless otherwise indicated in the parameter field of the table below.
Parameter Nominal voltage, UN Full-scale voltage, UFS Nominal Value 230V, 1% 270V 80A 5A 50.0 Hz, 0.3% 1 less than 2% less than 20% 23C, 2C 3.2768 MHz
Calibration Characteristics
Parameter Gain Calibration Calibration Range Calibration Resolution Phase Calibration Calibration Range Calibration Resolution Offset Calibration, Active Power Calibration Range Calibration Resolution Range,% of Full Scale Phase Power Offset Calibration, Reactive Power Calibration Range Calibration Resolution Range,% of Full Scale Phase Power 98.7 0.7712 0.457 VAr VAr % 89.8 0.7015 0.4157 W W % 5.625 0.044 degree degree 20 0.16 % % Min Typ Max Units
Full-scale current, IFS Base current, IB Frequency, f Power factor, PF Harmonic contents of voltage Harmonic contents of current Temperature, T AT73C500 master clock
24
AT73C500
AT73C500
The measurements are done according to IEC1036 specification. The results are averaged over a period of 10s. Before measurements, AT73C500 devices have been operational for minimum 1h.
Measurement Bandwidth Parameter General, 50 Hz line frequency - high limit (-3dB) - low limit (-3dB) Reactive Power and Energy, Voltage and Current Measurement - high limit - low limit Line Frequency - high limit - low limit Maximum Error Current 0.05IB 0.1IB...IFS 0.1IB 0.2IB...IFS 0.1IB 0.2IB...IFS 0.2IB...IFS Voltage UN UN UN UN UN UN UN Power Factor 1.000 1.000 0.5 lagging 0.5 lagging 0.8 leading 0.8 leading 0.25 lagging Min -0.4 -0.2 -0.4 -0.4 -0.4 -0.4 -1.0 Typ Max +0.4 +0.2 +0.4 +0.4 +0.4 +0.4 +1.0 Units % % % % % % % 350 20 Hz Hz 0.1IB 360 40 Hz Hz Current 0.1IB Voltage 0.9UN... 1.1UN 0.9UN... 1.1UN 750 30 Hz Hz Min Typ Max Units Current 0.1IB...IFS 0.1IB...IFS Voltage UN UN
Effect of Crosstalk The error caused by crosstalk from one current input to other two current inputs when the meter is carrying a single-phase load.
Single-Phase Load Error Power Factor 1.000 0.5 lagging Min -0.5 -0.5 Typ Max +0.5 +0.5 Units % %
Influence Quantities The additional error caused by different influence quantities.
Voltage Variation Error Power Factor 1.000 0.5 lagging Min -0.2 -0.2 Typ Max +0.2 +0.2 Units % %
25
Frequency Variation Error Frequency 0.95fN...1.05fN 0.95fN...1.05fN 0.8fN...5fN 0.8fN...5fN Current 0.1IB 0.1IB 0.1IB 0.1IB Voltage UN UN UN UN Power Factor 1.000 0.5 lagging 1.000 0.5 lagging Min -0.2 -0.2 -5.0 -5.0 Typ Max +0.2 +0.2 +0.5 +0.5 Units % % % %
Harmonic Distortion Error Current 40% of 5 harmonic in current
th
Voltage 10% of 5 harmonic in voltage
th
Min -0.5
Typ
Max +0.5
Units %
Reversed Phase Sequence Error Current 0.1IB Voltage UN Min -0.3 Typ Max +0.3 Units %
Voltage Unbalance Error Current 0.1IB Voltage One or two phases carry 0V Min -0.4 Typ Max +0.4 Units %
DC Component in Current Error Current IDC=0.1IFS Voltage UN Min -0.5 Typ Max +0.5 Units %
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AT73C500
AT73C500
Starting Current As default, the starting current is based on 5A basic current and 80A full scale current range.
Starting Current Voltage UN Min Typ Max 0.004 Units IB
Table Apparent Power and Energy Measurement
Apparent Power and Energy Error Current 0.05IFS...IFS 0.005IFS...0.05IFS 0.001IFS...0.005IFS Min -0.5 -2.0 -5.0 Typ Max +0.5 +2.0 +5.0 Units % % %
Temperature Coefficient Measured with the internal reference voltage source of AT73C501/AT73C502.
Mean Temperature Coefficient Current 0.1IB...IFS 0.1IB...IFS Voltage UN UN Power Factor 1.000 0.5 lagging Min Typ 0.02 0.02 Max 0.04 0.04 Units %/K %/K
The accuracy of Power Factor measurements was tested with PF values 0.5, -0.5, -1 and 1. Table Power Factor Measurement
Power Factor Error Current 0.05IFS...IFS 0.005IFS...0.05IFS Min -0.5 -2.5 Typ Max +0.5 +2.5 Units % %
Other Parameters The accuracy of the following parameters is measured in the conditions below unless otherwise indicated in the parameter field of the table. The measurement error has been calculated based on values averaged over 1min period.
Parameter Nominal voltage, UN Full-scale voltage, UFS Full-scale current, IFS Base current, IB Frequency, f Power factor, PF Harmonic contents of voltage Harmonic contents of current Temperature, T AT73C500 master clock Nominal Value 230V, 1% 270V 80A 5A 50.0 Hz, 0.3% 1 0% 0% 23C, 2C 3.2768 MHz
Table Phase Voltage Measurement
Phase Voltage Error Voltage 0.2UFS...UFS Min -0.5 Typ Max +0.5 Units %
Table Phase Current Measurement
Power Factor Error Current 0.05IFS...IFS 0.005IFS...0.05IFS Min -0.5 -2.5 Typ Max +0.5 +2.5 Units % %
Table Frequency Measurement
Frequency Error Frequency 40 Hz...100 Hz Min -0.5 Typ Max +0.5 Units %
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Digital Characteristics
VDD = 5V, VDA = 5V
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage, ISOURCE = -100 A Low-Level Output Voltage, ISINK = 0.5 mA Input Leakage Current -10 4.0 0.4 10 Min 4.0 1.0 Typ Max Units V V V V A
Crystal Oscillator
Parameter Crystal Frequency Crystal Inaccuracy Crystal Temp Coefficient (-25C...+70C) Min 1.0 Typ Max 6.0 30 30 Units MHz ppm ppm/C
AC Parameters
Parameter Master Clock Frequency Clock Duty Cycle at XI pin Min 1.0 40 Typ Max 6.0 60 Units MHz %
Timing of 8-bit Bus
Parameter DDLY DH SDLY SH ASU AH RWSU RWH BRS Parameter Data Delay from Falling Edge of STROBE Data Hold Time From Rising Edge of STROBE Strobe Delay from Falling Edge of Clock Strobe Hold Time From Rising Edge of Clock Addr Setup Time to Rising Edge of STROBE Addr Hold Time From Rising Edge of STROBE RD/WR Setup to Rising Edge of STROBE RD/WR Hold from Rising Edge of STROBE BRDY Set-Up Time to Rising Edge of Clock 5 0 3 10 3 10 3 40 20 20 Min Typ Max 25 Units ns ns ns ns ns ns ns ns ns
Power Supply Characteristics
Parameter VDD, VDA IDD (AT73C501/AT73C502 + AT73C500) IDA (ADC) AGND VREF-AGND Parameter Supply Voltage Supply Current 15 Supply Current Analog Ground Voltage Reference Voltage 2.45 1.17 10 2.5 1.27 22 15 2.55 1.37 mA mA V V Min 4.75 Typ Max 5.25 Units V
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AT73C500

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